As semiconductor technology provides end-user access to even larger amounts of user-defined logic (e.g., programmable logic devices, field programmable gate arrays, or gate arrays), it has become desirable to integrate multiple disjoint functions onto a single chip. This trend has, in turn, created a need for on-chip communications among these functions. It is therefore desirable to have a user-defined logic device which enables multiple disjoint functions to be implemented on a single chip, while facilitating on-chip communication among these various functions. It is also desirable for the user-defined logic device to provide an interface to a standard external bus system.
One type of user-defined logic device is a field programmable gate array (FPGA). Conventional FPGAs include circuitry which is initially programmed (or configured) in response to an externally provided stream of data values which is commonly referred to as a configuration data stream or bitstream. The programmable circuitry typically includes a plurality of configurable logic blocks (CLBs) and programmable interconnect circuitry, which will hereinafter be collectively referred to as a programmable logic array.
The programmable logic array can be programmed to implement a bus interface circuit and a function in response to the configuration data stream. Such a bus interface circuit enables the function to be operably coupled to a conventional external bus, such as a PCI bus. However, a significant portion of the FPGA's resources are required to create the bus interface circuit. For example, more than 40 percent of the CLBs of a typical FPGA may be required to create a bus interface circuit. It would therefore be desirable to have an FPGA architecture which is capable of operating from a conventional external bus, without requiring a substantial portion of the programmable logic array to establish a bus interface circuit.